Inversion-tolerant random error correcting digital data transmission system

ABSTRACT

A digital data transmission system is disclosed which decodes received error correction coded digital signals properly, irrespective of whether or not the polarities of these signals have become inverted during transmission or reception. The system thus permits a 180* phase ambiguity in the reinsertion of a regenerated suppressed carrier or subcarrier signal in the receiver, thereby simplifying the receiver in addition to correcting errors to improve the reliability of data transmission. The disclosed decoder circuitry includes a plurality of modulo 2 adder circuits for generating a plurality of estimators each of which is the mod 2 sum of an even number of the received digits. These estimators are fed to a threshold decision circuit which provides a serial readout of the decoded digits. The threshold decision circuit may consist of a simple majority decision circuit or a multiple input threshold circuit with either equal or unequal weighting factors on its input estimators.

United States Patent 13,577,186

[72] Inventor Michael E. Mitchell 3,398,400 8/ 1968 Rupp et al. 340/146.1

Syracuse, N.Y.

[21 App]. No. 828,485

[22] Filed 7 May 28, 1969 [45] Patented May 4, 1971 [73] AssigneeGeneral Electric Company Primary Examiner-Malcolm A. Morrison AssistantExaminerCharles E. Atkinson AttorneysNorman C. Fulmer, Carl W. Baker,Frank L. Neuhauser, Oscar B. Waddell and Joseph B. Forman [54]INVERSIONTOLERANT RANDOM ERROR ABSTRACT: A digital data transmissionsystemis disclosed CORRECTING DIGITAL DATA TRANSMISSION Wl'llCh decodesreceived error correction coded d gital signals SYSTEM properly,irrespective pf whether or not the polarities of these 4Claims 1 DrawingFig. signals have become inverted during transmission or reception. Thesystem thus permitsa 180 phase ambiguity in the [52] 1.8. C] 340/1461,einsertion of a regenerated suppressed carrier or subcarrier signal inthe receiver, thereby simplifying the receiver in addi- [5 ll Int. ClG086 25/00, tion t correcting errors to improve the reliability of dataH041 transmission. The disclosed decoder circuitry includes a plu- [50]Field Of Search 340/ 146.1; lit of modulo 2 adder circuits forgenerating a plurality of 179/15; 325/49, 56, 53 estimators each ofwhich is the mod 2 sum of an even number of the received digits. Theseestimators are fed to a threshold [56] References Cited decision circuitwhich provides a serial readout of the decoded UNITED STATES PATENTSdigits. The threshold decision circuit may consist of a simple 3,088,0694/ 1963 Markey 325/49 majority decision circuit or a multiple inputthreshold circuit 3,164,804 1/ 1965 Burton et al. 340/146. 1 with eitherequal or unequal weighting factors on its input estii,303,333 2/1967Massey 340/l46.lX mators.

22 CODED 2| l 26 Q INPUT DEMODULATOR FLO Rz|RealmsIRMIRIIIRIQIRWIRMlmalm:RulfllolmlmlmlmlflalmlRalRzIRT|- RECEIVERCARRIER '28 l l 1 l l l i l l l l l i l l i 3| """mssnnom I SH'FTDECODED INVERSION-TOLERANT RANDOM ERROR CORRECTING DIGITAL DATATRANSMISSION SYSTEM BACKGROUND OF THE INVENTION The invention is in thefield of electronic systems for the transmission of information in theform of coded digital signals. The invention is particularlyadvantageous in sup-' pressed-carrier communication systems for thetransmission of coded digital signals representing information such ascomputer data, telemetry information (for rockets and space stations,for example), stock market quotations, airline reservations, and otherbusiness and scientific data.

A frequently used technique for transmitting information, is to convertthe information into a binary form consisting of 1 bits and bits. Thesebits are frequently grouped into binary data words representing theelemental units of data to be transmitted. The type of coded informationtransmission system to which the invention best applies, employs anencoder at the transmitter which appends a number of extra (redundant)bits to each binary data word to form a code word for transmission, andemploys a decoder at the receiver which decodes the received codedsignals to recover the data words. Numerous error-correcting codes havebeen devised, having the general characteristic of adding redundant bitsto the data words according to systematic rules so as to form code wordssuch that, if during transmission a limited number of the bits in a codeword becomes altered or obliterated due to static, noise, fading orother causes, the received code word will nonetheless differ from anyother code word in a sufficient number of bits so that the decoder willbe able to properly decode it into the correct binary data word.

One type of error-correcting system, described in US. Pat. No. 3,237,160to Michael E. Mitchell and assigned to the same assignee as the presentinvention, employs a decoder at the receiver which functions to compareeach incoming word with a code word vocabulary. By the process ofcorrelation, the correct (or most likely correct) binary data word isselected and fed out of the decoder.

Another general type of error-correcting system, to which the presentinvention belongs, is described in US. Pat. Nos. 3,164,804 and 3,222,644to Burton and Mitchell and assigned to the same assignee as the presentinvention. In this type of system, each received binary word issequentially fed into a register, and estimator logic circuits generateoutput signals (estimators) in accordance with the contents of certainstages of the register. A majority logic circuit provides an output bitin accordance with the majority of the estimators. The register is thenshifted one step and the foregoing sequence repeated, and so on, wherebythe decoded data-word bits are obtained and fed out from the decoder.

For efficient transmission of the coded binary words via radio waves,over telephone lines, or other media (such as magnetic tape), suppressedcarrier techniques are a'dvantageously employed so that more of theavailable energy can be used for transmission of the modulationinformation and less energy is wasted on transmission of a carrier.However, in receivers that require a reconstituted carrier to begenerated in correct phase with the suppressed carrier for achievingproper demodulation, it is necessary to transmit a residual carrier,subcarrier, or pilot signal for maintaining the correct phase of theregenerated carrier. If this proper phasing is not maintained, thedemodulated digits can become inverted (complemented), and unless ameans is provided for detecting this event, the output of thedemodulator will be ambiguous. Such transmission of a residual carrier,or subcarrier, or pilot signal, undesirably increases the complexity ofthe system and also reduces the amount of available energy that can beutilized for transmitting the useful modulation information. Attempts toincrease the relative amount of energy in the modulation increases theerror probability and delay in detecting the proper carrier phase,particularly at the lower signalto-noise ratios. The foregoingdifficulties of suppressed carrier techniques also arise if suppressedsubcarriers are utilized with, or in lieu of, suppressed carriertransmission. The alternative of using differentially coded transmission(such as by representing a l with a phase shift and a 0 with the absenceof a phase shift) has been extensively used as a means of resolving thel-0 ambiguity without transmitting residual carrier or other referencesignals. However, it is a well-known fact that this last alternative canconvert isolated bit errors into double adjacent bit errors. It is alsowell known that differentially coherent recovery of the received digitscauses an objectionable degradation in receiver performance. Thosefamiliar with the state of the art in this field are keenly aware of theneed for a practical technique capable of fully realizing the advantagesof suppressed carrier transmission.

SUMMARY OF THE INVENTION Objects of the invention are to provide animproved errorcorrecting coding system, and to provide such a systemwhich is inversion tolerant whereby proper decoding is achieved vw'thoutresorting to differential coding or differentially coherent demodulationand without the necessity of providing any residual carrier, subcarrier,pilot signal, or other special phasing means for reinsertion of aregenerated carrier.

The invention comprises, briefly and in a preferred embodiment, a signalcoding and transmission system for digital error correction code wordsof the appropriate type, comprising a decoder provided with a pluralityof modulo 2 adder circuits each of which adds different combinations ofan even number of bits selected from the received code word, wherebyeach of said adder circuits produces a separate estimate of the samecode bit, and a threshold decision device (such as a majority logiccircuit) which uses the estimates to decide on the likely value of thetransmitted code bit. A decoder timing circuit provides shift pulses soas to iterate the estimation, decision and readout of successive decodedbits. The invention also comprises, in combination with the foregoing, asuppressed carrier or other equivalent means for transmitting andreceiving code words with an allowed l-O ambiguity in the decoder input,such as is provided by double-sideband suppressed-carrier transmissionfrom a phase-reversal-keyed transmitter together with quasi-coherentsynchronous detection using a regenerated carrier having an allowed 180phase ambiguity.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is an electrical block diagramof a transmitter in accordance with a preferred embodiment of theinvention, and

FIG. 2 is an electrical block diagram of a receiver in accordance withthe preferred embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT In the transmitter circuit ofFIG. 1, a plurality of binary data bits a through a are respectivelyapplied to stages R through R of a shift register 11. The contents ofstages of R R R and R are fed to a modulo 2 adder 12, the output ofwhich is fed into stage R of the shift register 11, The input data bitsa through a each constitutes a binary l or 0, in standard binaryparlance. The mod 2 adder 12 provides the mod 2 sum of the binaryinputs. As is well known, mod 2 addition is the same as binary additionexcept that carries are ignored. The symbol for mod 2 addition is EB andthe possible summations of the various combinations of binary inputs areas follows:

v The arrangement of the shift register 11 and mod 2 adder 12 of 21'bits per coded word, of which the first 11 bits are data bits and theremaining are redundant bits added for coding purposes. The shiftregister 11 is sequentially shifted toward the right under control of atiming-circuit 15, a step at a time, to produce the aforesaid codedoutput at 14. The aforesaid Pat. No. 3,222,644 shows and describes inmore detail an arrangementfor producing any word of the (15, 7) code.The code words-comprising various other codes can be' similarlyproduced.

The binary code words at the output 14 of i the encoder 13 are fed to asuppressed-carrier modulator 16 which modulates a carrier or subcarrier,provided by a carrier generator '18, with the data bits andsimultaneously or subsequently suppresses the carrier or'subcarrier.Multiple information channels may be achieved by employing a combinationof carriers and associated subcarriers. For convenience, the termcarrier as used herein will be understood to include the substitution oraddition of one or more subcarriers. Supressed-carrier modulation isprovided at the output 17 of the suppressed-carrier modulator 16. Inaccordance with a feature of the invention, no residual carrier, pilotsignal, nor other carrier reinsertion phasing signal need be provided atthe transmitter output 17. The transmitter output at 17 is transmittedby suitable means, such as radio waves or telephone wires, to areceiver.

In the receiver of FIG. 2, the .signal received from the transmitter ofFIG. 1 is fed, after detection and amplification if required, to theinput 21 of a demodulator 22 to which a regenerated carrier signal isinserted at 23, from a synchronized local oscillator circuit 24. Thelocal oscillator is synchronized to the frequency of the suppressedcarrier of received signal 21, but the local oscillator phase is allowedto be either 0 or 180 relative to the suppressed-carrier phase. Theoutput of the demodulator, at 26, consists of the demodulated bits to befed to the decoder. In this example, the output 14 of the encoder 13 isa word of the (21, 11-) code. Since no carrier insertion phasing meansis required nor provided in the system of the invention, the l' and 0hits at the output 26 of the demodulator 22 will be the same, except fortransmission errors, as the l and 0 bits provided at the output 14 ofthe encoder 13 only at times when the carrier insertion 23 happens to bein phase, or approximately in phase, with the suppressed carrier ofreceived signal 21. At other times this relationship will be inverted(complemented); i.e., except for transmission errors, 1's will appear atdemodulator output 26 corresponding to Us at the encoder output 14, and,conversely, US will appear at output 26 of demodulator 22 correspondingto ls at output 14 of encoder 13, at times when the carrier insertion at23 is 1809 out of phase or approximately 180 out of phase with thesuppressed carrier of the received signal 21. In prior art systems thisinversion of the demodulated bits with no indication of-its occurrenceis intolerable; however, in accordance with feature of the invention,the aforesaid inversion of demodulated bits is of no consequence,because the decoder will provide proper decoded data bits irrespectiveof complementing or inversion of the received code word bits.

An electronic switch 27 is arranged to temporarily connect the output 26of demodulator 22 to the input 28 of a 21 stage shift register 29,whereupon the 21 stages of shifi register 29 become loaded with the 21bits of a received code word. The switch 27 then connects the shiftregister input 28 to the output 31 thereof, to provide a feedback loopfor sequentially shifting the received word bits from the output to theinput of the shift register 29. Five modulo '2 adder circuits 35, 36,37, 38, and 39 are provided. Four different stages of the shift register29 are connected to each of the modulo 2 adders 35- .-39, as shown inFIG. 2. The outputs of the five modulo 2 adders 35-39, are connected toinputs of a threshold decision circuit 41, which may comprise majoritylogic circuit, the output 42 of which is a sequential readout of thedecoded binary data word bits which, in the example shown, is 1 1 bitsper data word. If one or two of the input bits to the decision circuit41 a are erroneous, due to interference or for other reasons themajority logic will, on the basis of the remaining three correct inputbits, provide the correct outputbit. After each majority logic decision,the shift register 29 is shifted one stage, and the procedure isrepeated. After a received code word has been decodedand the decodeddata word has been read out, the switch 27 functions to load anotherreceived code word into the shift register 29, and so on. The aforesaidswitching and shifting is controlledby a decoder timing circuit 30. Inthe arrangement shown, the contents of stage R of shift register 29 isnot fed to an adder circuit because the connections as shown from stagesR through R of the shift register 29 to the adder circuits .35-39 aresufficient to insure that received code words with up to two bit errorsare properly decoded and read out at the majority logic output 42, evenif such words have been complemented.

In accordance with a feature of the invention, the contents of an evennumber of stages of the shift register 29 are fed to each of the modulo2 adder circuits 35'through 39. By so doing, the modulo 2 sum output ofeach of the adder circuits will be unaffected by inversion orcomplementing of the bits fed into the adders. This is illustrated bythe following example of modulo Z'addition, in which although the fourbits of the righthand column are inversions of. the four bits of theleft hand column, nevertheless the resulting modulo 2 addition remainsthe same:

l The following example shows how an odd number of bits can result indifferent sums if the bits are inverted:

Since the arrangement of the invention results in an inversion tolerantsystem, correct functioning of the circuit will be unafiected by whetheror not the carrier inserted at 23 is'in phase or 180 out of phase withthe suppressed carrier at 21, and therefore the system of the inventionfunctions properly without the necessity for transmitting anyphase-correcting signal. If the carrier insertion at 23 is in phase withthe suppressed carrier, the bits fed into shift register 29 will be thesame polarity (except for bit errors) as the bits in the transmittedcode word; if the carrier insertion at 23 is in reversed phase with thesuppressed carrier, these bits will be inverted, but this is of noconsequence for successful functioning of the circuit, as has beenexplained above. So long as the inserted carrier at 23 has the samefrequency of the suppressed carrier, the circuit will function properlyregardless of whether it is in phase or 180 out of phase with thesuppressed carrier. However, there may occasionally be an inversionoccurring near the middle of a received code as it enters shift register29, whereupon there will be decoding error since the polarity of thebits in the first and second parts of the received word will beopposite. However, the frequency of this occurrence can be made at leastas low as the frequency of occurrence of a lphase error in thereinserted carrier due to obliteration of the phasing signal by staticor other interference in prior art systems.

While a' preferred embodiment of the invention has been shown anddescribed, various other embodiments and modifications thereof willbecome apparent to persons skilled in the art, and will fall within thescope of the invention as defined in the following claims.

. of "the type having a-t'ransmitter and a'ireceiver, said trans mitt'erincluding an encoder for'encoding the data bits to be transmitted intoan error correcting code word containing redundant bits'andsuppressed-carrier modulator means for providing a transmitted signalhaving modulation in accordance with said code word, and said receiverincluding means for demodulating said transmitted signal and decodermeans for decoding the demodulated signal, said decoder means comprisinga multiple stage shift register for accommodating the demodulated codebits of a word wherein the improvement comprises a plurality of modulo 2adders each having input connections to an even number of stages of saidshift register, and a threshold decision circuit connected to' receivethe outputs of said modulo 2 adders, said modulo 2 adders which areconnected to an even number of shift register stages constituting theonly modulo 2 adders connected between said shift register and saidthreshold decision circuit,

said receiver including a carrier insertion means connected to saidsignal demodulating means, and in which .no additional synchronizingsignal is provided between said transmitter and said receiver forcontrolling the phase of the receiver inserted carrier with respect tosaid suppressed carrier.

2. A system as claimed in claim 1, for use with the (21, ll) code, inwhich said shift register comprises 2l stages, and comprising five ofsaid modulo 2 adders each having four inputs, means connecting theinputs of a first of said adders respectively to stages 3, 8, 9, and 12of said shift register,

means connecting the inputs of a second of said adders respectively tostages 6, 7, 10, and of said shift register, means connecting the inputsof a third of said adders respectively to stages 2, 5, l5, and 17 ofsaid shift register, means connecting the inputs of a fourth of saidadders respectively to stages 4,

l3, l8, and 19 of said shift register.

3. A decoder for decoding code words transmitted without a subcarriersignal and demodulated in a receiver by insertion of a regeneratedcarrier signal, comprising a multiple stage shift register and means forfeeding a received code work into said shift register, wherein theimprovement comprising a plurality of modulo 2 adders each having inputconnections to an even number of stages of said shift register, and athreshold decision circuit provided with inputs and an output, saidinputs connected to receive the outputs of said modulo 2 adders, saidmodulo 2 adders being connected to an even number of shift registerstages and constituting the only modulo 2 adders connected between saidshift register and said threshold decision circuit to produce thedecoded output signal at said'output of said threshold decision circuitindependent of the phase of the regenerated carrier signal in saidreceiver.

4. A system asclaimed in claim 3, for use with the (21, 11) code, inwhich said shift register comprises 21 stages, and comprising five ofsaid modulo 2 adders each having four inputs, means connecting theinputs of a first of said adders respectively to stages 3, 8, 9, and 12of said shift register, means connecting the inputs of a second of saidadders respectively to stages 6, 7) l0, and 20 of said shift' register,means connecting the inputs of a third of said adders respectively tostages 2, 5, l5,.and 17 of said shift register, means connecting theinputs of a fourth of said adders respectively to stages 4, l4, l6, and21 of said shift register, and means connecting the inputs of the fifthone of said adders respectively to stages 11, 13, 18, and 19 of saidshift register.

1. A coded error-correcting digital data transmission system of the typehaving a transmitter and a receiver, said transmitter including anencoder for encoding the data bits to be transmitted into an errorcorrecting code word containing redundant bits and suppressed-carriermodulator means for providing a transmitted signal having modulation inaccordance with said code word, and said receiver including means fordemodulating said transmitted signal and decoder means for decoding thedemodulated signal, said decoder means comprising a multiple stage shiftregister for accommodating the demodulated code bits of a word whereinthe improvement comprises a plurality of modulo 2 adders each havinginput connections to an even number of stages of said shift register,and a threshold decision circuit connected to receive the outputs ofsaid modulo 2 adders, said modulo 2 adders which are connected to aneven number of shift register stages constituting the only modulo 2adders connected between said shift register and said threshold decisioncircuit, said receiver including a carrier insertion means connected tosaid signal demodulating means, and in which no additional synchronizingsignal is provided between said transmitter and said receiver forcontrolling the phase of the receiver inserted carrier with respect tosaid suppressed carrier.
 2. A system as claimed in claim 1, for use withthe (21, 11) code, in which said shift register comprises 21 stages, andcomprising five of said modulo 2 adders each having four inputs, meansconnecting the inputs of a first of said adders respectively to stages3, 8, 9, and 12 of said shift register, means connecting the inputs of asecond of said adders respectively to stages 6, 7, 10, and 20 of saidshift register, means connecting the inputs of a third of said addersrespectively to stages 2, 5, 15, and 17 of said shift register, meansconnecting the inputs of a fourth of said adders respectively to stages4, 14, 16, and 21 of said shift register, and means connecting theinputs of the fifth one of said adders respectively to stages 11, 13,18, and 19 of said shift register.
 3. A decoder for decoding code woRdstransmitted without a subcarrier signal and demodulated in a receiver byinsertion of a regenerated carrier signal, comprising a multiple stageshift register and means for feeding a received code work into saidshift register, wherein the improvement comprising a plurality of modulo2 adders each having input connections to an even number of stages ofsaid shift register, and a threshold decision circuit provided withinputs and an output, said inputs connected to receive the outputs ofsaid modulo 2 adders, said modulo 2 adders being connected to an evennumber of shift register stages and constituting the only modulo 2adders connected between said shift register and said threshold decisioncircuit to produce the decoded output signal at said output of saidthreshold decision circuit independent of the phase of the regeneratedcarrier signal in said receiver.
 4. A system as claimed in claim 3, foruse with the (21, 11) code, in which said shift register comprises 21stages, and comprising five of said modulo 2 adders each having fourinputs, means connecting the inputs of a first of said addersrespectively to stages 3, 8, 9, and 12 of said shift register, meansconnecting the inputs of a second of said adders respectively to stages6, 7, 10, and 20 of said shift register, means connecting the inputs ofa third of said adders respectively to stages 2, 5, 15, and 17 of saidshift register, means connecting the inputs of a fourth of said addersrespectively to stages 4, 14, 16, and 21 of said shift register, andmeans connecting the inputs of the fifth one of said adders respectivelyto stages 11, 13, 18, and 19 of said shift register.